The present invention relates in general to a method of fabricating semiconductor devices and in particular to BICMOS or bipolar technologies.
The availability of PNP transistors with a performance comparable to NPN transistors in a BICMOS or bipolar technology provides a considerable advantage in the design of analog and digital circuits. The bandwidth of operational amplifiers (OpAmps) is typically limited by the output stage. The use of a high performance PNP in the level shift and output stages can improve the performance of OpAmps considerably (especially those with capacitive loads). Some other analog circuits benefit from the complementary NPN and PNP transistors, such as phase locked loop circuits, D/A converters, voltage regulators, high speed comparators, charge pump circuits and video amplifiers. In digital circuits, since both PNP and NPN transistors are involved during pull-up and pull-down stages of switching, the slower device determines the performance limits of the circuit. As a result, the use of a PNP transistor with a performance comparable to NPN will considerably improve the overall performance of the circuit. Another application of the complementary BICMOS technology is the full swing BICMOS logic circuits, with a performance leverage over the conventional BICMOS circuits for reduced power supply voltage operation.
In the conventional processes, the only available PNP transistors are lateral PNP and common collector substrate PNP. The relatively large basewidth, and a result, lower cutoff frequency of lateral PNP transistors causes a limitation in the design of high performance circuits. On the other hand, even though substrate PNPs exhibit relatively higher cutoff frequencies, they suffer from being common collector devices and are limited to certain applications.
Therefore, the effort of incorporating high speed isolated vertical PNP transistors with high current drive capability in the same BICMOS or bipolar process with high performance NPN transistors is well justified. On the other hand, the combination of analog, digital and programmable memory functions on a single chip is needed for the system level applications. A further requirement is the combination of high and low voltage devices in the same chip. The availability of such a multitude of device types makes possible the integration of a complete system on a single chip.
In the prior art, the methods of forming complementary MOS (CMOS) transistors at the same time as NPN, lateral PNP and substrate PNP transistors are well known. Some methods of forming complementary NPN and PNP transistors in the same process as CMOS transistors are also known. However, the BICMOS or complementary BICMOS processes which are developed from the bipolar technologies are usually penalized with lower performance CMOS. Furthermore, the complementary BICMOS processes in the prior art do not offer the flexibility, performance and the variety of devices on the same substrate as offered by the present invention.
The following is a list of the references on the complementary BICMOS and complementary bipolar technologies with isolated vertical PNPs:
1. K. Soejima, A. Shida et al., "A BICMOS technology with 660 MHz vertical PNP transistor for Analog/Digital ASICs", IEEE JSSC, Vol. 25, April 1990. PA0 2. D. de Lang, E. Bladt et al., "Integration of Vertical PNP Transistors in a Double-Polysilicon Bi-CMOS Process", 1989 Bipolar Circuits and Technology Meeting, p.190, Minnesota, 1989. PA0 3. J. Kendall, B. Rioux, L. Bourbonnais et al., "BANCMOS: A 25 V Analog-Digital BICMOS Process", 1990 Bipolar Circuits and Technology Meeting, p.86, Minnesota, 1990. PA0 4. L. Hutter, J. Trogolo, "Method of Making Vertical PNP in Merged Bipolar/CMOS Technology", U.S. Pat. No. 4,855,244. PA0 5. K. Ratnakumar, "Method of Making a Complementary BICMOS Process With Isolated Vertical PNP Transistors", U.S. Pat. No. 5,011,784. PA0 6. S. Mastroianni, "Merged Complementary Bipolar and MOS Means and Method", U.S. Pat. No. 4,830,973. PA0 7. D. Aull, A. Spires, P. Davis, S. Moyer, "A High-voltage IC for a Transformerless Trunk and Subscriber Line Interface", IEEE JSSC, Vol.16, August 1981. PA0 8. T. Kikkawa, T. Suganuma et al., "A New Complementary Transistor Structure for Analog Integrated Circuits", IEDM-80, p. 65, 1980. PA0 9. A. Feygenson et al., "CBIC-V, a New Very High Speed Complementary Silicon Bipolar IC Process", 1989 Bipolar Circuits and Technology Meeting, p. 173, Minnesota, 1989.